1. Field of the Invention
The present invention generally relates to an apparatus for providing a communication link between a high performance packet switching mechanism and a main processor, an improved method of managing first-in-first-out buffers in the main processor, an error detection circuit of the apparatus and an improved clock fault detection circuit for the apparatus.
2. Description of the Related Art
In parallel processing systems, the system performance is dependent upon processor performance and communication performance. Communication performance is of paramount importance and is divided into two components: latency and bandwidth. Both components must be optimized to produce an efficient communication subsystem.
In conventional systems, apparatus such as adaptors have been used between a main processor (e.g., a RISC System/6000 processor or the like) and a high performance switching (HPS) mechanism. However, these adaptors require that the main processor be involved in all data movement across a relatively slow bus. Thus, while data transfer is occurring, the main processor has been unable to perform other tasks. This is a problem and does not allow optimization of the main processor.
A related problem has been that in the conventional systems, in which a coprocessing mechanism is used on the adaptor to resolve the previous concern, unnecessary traffic has been conducted across a relatively slow bus between the main processor and the coprocessing mechanism, so that not all the cycles available on that bus are used for moving application data. This reduces the communications efficiency of the system.
Further, the conventional systems have employed polling (for communication tasks) across this relatively "slow" bus (e.g., from the main processor to the coprocessing mechanism and vice versa) which slows down the main processor and utilizes valuable bandwidth, thereby reducing the efficiency of the overall system, causing contention with application dam on the bus, increasing message latency, and decreasing message bandwidth. This degrades communication efficiency.
Further, the conventional adaptor has been operable only in a slave mode. That is, it has been unable to initiate data transfers. This is a problem since the main processor must be the master (e.g., initiator) and thus, as mentioned above, must be integrally involved throughout the entire data transfer process.
Another problem is checking the routing (and thus integrity) of the dam. In a parallel system using a message passing protocol, packets of information are passed between processors in the system. These data packets usually have headers which contain routing information that guide the packets from the source processor through the network fabric to the destination processor. In some systems, the route information is consumed by the network fabric (e.g., data bits are "dropped off" as they progress along the data path) so that when the message packet reaches its destination the route information no longer exists. If the route data is corrupted, the network may not detect an error and a packet could get routed to the wrong destination processor, thereby resulting in a data integrity error.
Another problem has been that the conventional adaptor may hang up the main processor indefinitely should the adaptor clock fail.
Further, conventional adaptors perform communication rusks using fixed means that are difficult to change should they prove inefficient.